Dynamic program window determination in a memory device

ABSTRACT

A memory device has a controller. The controller is configured to cause the memory device to inhibit programming of a group of memory cells. The controller is configured to cause the memory device to apply a programming pulse to control gates of the group of memory cells. The controller is configured to determine an amount of disturb experienced by the group of memory cells responsive to the programming pulse. The controller is configured to determine a program window responsive to the amount of disturb.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.14/826,298, filed Aug. 14, 2015 (allowed), which application is adivisional of U.S. patent application Ser. No. 14/538,020, filed Nov.11, 2014 and issued as U.S. Pat. No. 9,129,684 on Sep. 8, 2015, which isa divisional of U.S. patent application Ser. No. 13/190,911, filed Jul.26, 2011 and issued as U.S. Pat. No. 8,902,648 on Dec. 2, 2014, whichapplications are commonly assigned and incorporated in their entiretyherein by reference.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory andmore particularly to programming memory devices.

BACKGROUND

Memory devices are typically provided as internal, semiconductor,integrated circuits in computers or other electronic devices. There aremany different types of memory including random-access memory (RAM),read only memory (ROM), dynamic random access memory (DRAM), synchronousdynamic random access memory (SDRAM), and non-volatile/flash memory.

Flash memory devices have developed into a popular source ofnon-volatile memory for a wide range of electronic applications. Flashmemory devices typically use a one-transistor memory cell that allowsfor high memory densities, high reliability, and low power consumption.Common uses for flash memory include personal computers, personaldigital assistants (PDAs), digital cameras, and cellular telephones.Program code and system data such as a basic input/output system (BIOS)are typically stored in flash memory devices for use in personalcomputer systems.

Each cell in a non-volatile memory device can be programmed as a singlebit per cell (i.e., single level cell—SLC) or multiple bits per cell(i.e., multilevel cell—MLC). Each cell's threshold voltage (V_(t))determines the data that is stored in the cell. For example, in an SLCmemory, a V_(t) of 0.5V might indicate a programmed cell while a V_(t)of −0.5V might indicate an erased cell. The MLC has multiple positiveV_(t) ranges that each indicates a different state whereas a negativeV_(t) range typically indicates an erased state. An MLC memory can takeadvantage of the analog nature of a traditional flash cell by assigninga bit pattern to a specific voltage range stored on the cell. Thecollection of different V_(t) ranges (each of which representing adifferent programmable state) together are part of a fixed programwindow that encompasses the fixed voltage range over which a memorydevice is programmable. Each of the ranges are separated by a voltagespace (“margin”) that is relatively small due to the limitations offitting a number of states into the program window of a typical lowvoltage memory device.

FIG. 1 illustrates a typical fixed program window 100 of a non-volatilememory device. The illustrated program window 100 encompasses sixprogrammable states L1-L6 such that the distributions 102-107 for allthe programmable states fit within the program window 100 (as usedherein, a “distribution” for a state refers to a number of cells havinga V_(t) within the particular range of V_(t)'s corresponding to thatstate). The program window 100 for a memory device is determined duringmanufacture of the device as a result of an engineering assessment. Theassessment determines a maximum V_(t) of the erased state distributionL0 101 and a minimum V_(t) of the “highest” distribution L7 108. Thestate L7 corresponding to the highest range of V_(t)'s may not be useddue to the relatively large voltages required to program this stateand/or the program disturb that can result from these programmingvoltages, in which case it is excluded from the fixed program window100, as illustrated in FIG. 1.

One problem with a fixed program window is that the programmingcharacteristics (maximum programmable voltage, number of programmingpulses required, speed of programming) of a memory device typicallychange as the memory experiences an increasing number of program/erasecycles. Also, the programming characteristics can vary between memorydies as well as between memory blocks and/or pages of each memory die.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art fora way to dynamically determine a program window in a memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a typical prior art fixed program window encompassingprogrammable states.

FIG. 2 shows a flowchart of one embodiment of a method for dynamicallydetermining a program window.

FIG. 3 shows a flowchart of one embodiment of a method for determining aprogram window in accordance with the method of FIG. 2.

FIG. 4 shows a flowchart of another embodiment of a method fordetermining a program window in accordance with the method of FIG. 2.

FIG. 5 shows a diagram of the effect of program disturb on an L0distribution.

FIG. 6 shows a block diagram of one embodiment of a memory systemincorporating the method for dynamic program window determination of thepresent disclosure.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference ismade to the accompanying drawings that form a part hereof and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims and equivalents thereof.

FIG. 2 illustrates a flowchart of one embodiment of a method fordynamically determining a program window in a memory device. Ameasurement is first performed to determine the width of the programwindow 201. This measurement can be done in many different ways. FIGS. 3and 4 illustrate two embodiments of performing this measurement.

The embodiments of FIGS. 3 and 4 are based on a measurement of an amountof program disturb experienced by one of the states (e.g., L0, erasedstate). The amount of program disturb corresponds to a certain programwindow (e.g., in Volts). Thus, once the amount of program disturb isdetermined, the corresponding program window can be determined through,for example, accessing a table with the amount of program disturb.

The program window measurement is performed dynamically unlike the priorart that determines the program window once such as during manufactureor design of the memory device. The present embodiment can perform thisdetermination during each program cycle so that, as the memory deviceprogramming characteristics change in response to an increasing numberof program/erase cycles, as well as other factors, the program windowcan be adjusted to track the changing programming characteristics.

In one embodiment, the program window determination is performed duringeach program operation. Other embodiments can perform the determinationperiodically after a particular number of program operations. Stillother embodiments can perform the determination aperiodically. In onesuch embodiment, the frequency of determinations is increased as thememory device experiences a greater number of program/erase cycles. Inanother aperiodic embodiment, the frequency of determinations isdecreased as the memory device experiences a greater number ofprogram/erase cycles.

In one embodiment, a new program window is determined for a certaingrouping of memory cells (e.g., page, block, array). Thus, each memorycell group can be associated with (e.g., assigned) a different programwindow since the programming characteristics can vary from page to pageand block to block.

After the new program window has been measured 201, an indication of theprogram window is stored within the measured memory cell group 203. Thenewly determined program window is thus associated with the memory cellgroup to which it applies.

FIG. 3 illustrates a flowchart of one embodiment for dynamicallydetermining the program window 201 in accordance with the method of FIG.2. This embodiment performs the determination after a coarse programmingoperation and before the fine programming begins. Thus, the new programwindow can then be used during the fine programming operation.

As is known in the art, a coarse programming operation initially moves athreshold voltage of memory cells being programmed more quickly bybiasing an access line (e.g., word line) coupled to control gates of thememory cells with a program voltage (V_(pgm)) that is increased with arelatively large step voltage. After the threshold voltage has eitherreached a target threshold voltage or is moved to within a certaindistance of the target threshold voltage, the coarse programming isended and fine programming is performed. The fine programming uses asmaller step voltage to more slowly increase the program voltage inorder to “fine tune” the threshold voltage and get it closer to thetarget threshold voltage without over-programming the memory cell. Anover-programmed memory cell has a threshold voltage that exceeds thetarget threshold voltage.

The dynamic program window measurement method of FIG. 3 initiallyperforms a coarse program operation 301. During this operation, some ofthe memory cells are inhibited from programming and are thus held in aninitial state (e.g., L0). However, these inhibited memory cells canstill experience a program disturb condition that can affect theirrespective current states. After the coarse program operation has beencompleted, an amount of program disturb experienced by the memory cellsthat are still in the particular state (e.g., L0) is determined.

Referring now to FIG. 5, after the coarse programming has beencompleted, it is possible to read all of the cell's threshold voltages(V_(t)) and store their values into a page buffer of the array. It isalso possible to define a specific threshold level (e.g., a delta abovethe maximum V_(t) 500 of the range of V_(t)'s corresponding to theinitial state L0 500, so that the number of L0 bits above the thresholdbefore coarse programming is zero). After the coarse programming, acontroller can determine the number of cells of the final L0distribution 501 with a V_(t)>threshold. This number is a measure of howmuch their threshold voltages have increased due to the program disturb.

The change in the particular state (e.g., L0) (e.g., program disturb)can then be used to access a table to determine an associated programwindow 305 (e.g., program window width). This width can be representedby a voltage or a digital indication of a voltage. In one embodiment,the table includes representations of the change in the particular stateeach with an associated program window width. In another embodiment, thetable includes a representation of the upper end of the final particularstate (e.g., L0) with an associated program window width.

FIG. 4 illustrates a flowchart of another embodiment for performing thedynamic determination of the program window 201 as discussed above withreference to FIG. 2. This embodiment is performed prior to any coarseprogramming or lower page programming of the group of memory cells to beprogrammed.

All of the data lines (e.g., bit lines) that are coupled to the group ofmemory cells being programmed are biased with an inhibit voltage 401(e.g., V_(CC) or supply voltage). A programming pulse is then applied tothe word lines 403 that are coupled to the control gates of memory cellsof the group of memory cells being programmed. Since the memory cellsare inhibited from being programmed, the programming pulse can beconsidered a dummy programming pulse in that the memory cells cannot beprogrammed in response to this pulse. However, the memory cells canexperience the program disturb condition as a result of this programmingpulse. The amount of program disturb experienced by a particular state(e.g., L0) is then determined 405. The amount of disturb can be used todetermine an associated program window. For example, the amount ofdisturb can be used to access a table for an associated program windowwidth (e.g., voltage) 407.

The amount of program disturb of the embodiment of FIG. 4 can bedetermined substantially similar to the process used in the embodimentof FIG. 3. Additionally, the embodiment of FIG. 4 can also be in thedigital domain or the analog domain.

As described previously with reference to FIG. 2, an indication of theprogram window that was determined from the amount of program disturbcan be stored in the group of memory cells to which the window applies.For example, if a page of memory cells is being programmed, theindication of the associated program window can be stored in the samepage. Thus, when the page is being read after the programming operation,the indication of the associated program window can also be read toassist in the read operation. For example, using the indication of theprogram window associated with the page being read, the controller canthen determine a respective voltage range in which each of theprogrammed states are located.

The method for dynamically determining a programming window can also beused as a form of wear leveling routine of a memory device. As is knownin the art, pages and/or blocks of memory cells of a memory device canexperience different amounts of program/erase cycles. Typical prior artwear leveling routines move data around the pages and/or blocks ofmemory cells and control the logical addressing of memory cells toattempt to equally distribute memory cell access so that the no one pageand/or block is overused.

The dynamic determination of the programming window for each page and/orblock of memory enables a controller (e.g., on die control circuitry oran external controller chip) to track the program window for the pageand/or block of memory as the window degrades. The controller can movethe data around to other memory pages and/or memory blocks based ontheir respective program windows. When a page and/or block of memory hasa program window that has degraded to the point where it can no longerbe used, that particular page and/or block of memory can be flagged asunusable. In one embodiment, the controller might flag the page and/orblock of memory to operate in an SLC mode instead of an MLC mode,assuming the program window is still wide enough to be used to store asingle state. The density could have a range of degradations (e.g., 3bits per cell, 2 bits per cell, SLC). The dynamic adjustment can be moreefficient. In another embodiment, the method for dynamic determinationof the programming window can be used to sort data into different pages.For example, the importance of data can be compared to the resiliency ofthe underlying block. The more important data can be moved to strongerblocks/pages as a part of the block cleanup activities.

FIG. 6 illustrates a functional block diagram of a memory device 600that can incorporate the memory cells of the present invention. Thememory device 600 is coupled to a processor 610. The processor 610 maybe memory controller, a microprocessor or some other type of controllingcircuitry. The memory device 600 and the processor 610 form part of amemory system 620. The memory device 600 has been simplified to focus onfeatures of the memory that are helpful in understanding the presentinvention.

The memory device includes an array of non-volatile memory cells 630that can be flash memory cells or other types of non-volatilesemiconductor cells. The memory array 630 is arranged in banks of rowsand columns. The control gates of each row of memory cells is coupledwith a wordline while the drain and source connections of the memorycells are coupled to bitlines. As is well known in the art, theconnection of the cells to the bitlines depends on whether the array isa NAND architecture or a NOR architecture. The memory cells of thepresent invention can be arranged in either a NAND or NOR architecture,as described previously, as well as other architectures.

An address buffer circuit 640 is provided to latch address signalsprovided on address input connections A0-Ax 642. Address signals arereceived and decoded by a row decoder 644 and a column decoder 646 toaccess the memory array 630. It will be appreciated by those skilled inthe art, with the benefit of the present description, that the number ofaddress input connections depends on the density and architecture of thememory array 630. That is, the number of addresses increases with bothincreased memory cell counts and increased bank and block counts.

The memory device 600 reads data in the memory array 630 by sensingvoltage or current changes in the memory array columns using senseamplifier/buffer circuitry 650. The sense amplifier/buffer circuitry, inone embodiment, is coupled to read and latch a row of data from thememory array 630. Data input and output buffer circuitry 660 is includedfor bi-directional data communication over a plurality of dataconnections 662 with the controller 610. Write circuitry 655 is providedto write data to the memory array.

Control circuitry 670 decodes signals provided on control connections672 from the processor 610. These signals are used to control theoperations on the memory array 630, including data read, data write, anderase operations. The control circuitry 670 may be a state machine, asequencer, or some other type of controller. The control circuitry 670is adapted to perform the programming window adjustment embodimentsdisclosed previously. The control circuitry 670 can be part of thememory device 600 as shown or separate from the memory device 600.

The flash memory device illustrated in FIG. 6 has been simplified tofacilitate a basic understanding of the features of the memory and isfor purposes of illustration only. A more detailed understanding ofinternal circuitry and functions of flash memories are known to thoseskilled in the art.

CONCLUSION

In summary, one or more embodiments of the present disclosuredynamically determine a program window for each page and/or block ofmemory. The program window can be determined during each programmingoperation by determining an amount of program disturb experienced by aparticular state and using that amount of program disturb to determinethe program window.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the invention. It is intended that this invention belimited only by the following claims and equivalents thereof.

What is claimed is:
 1. A memory device, comprising: a controller;wherein the controller is configured to cause the memory device toinhibit programming of a group of memory cells; wherein the controlleris configured to cause the memory device to apply a programming pulse tocontrol gates of the group of memory cells; wherein the controller isconfigured to determine an amount of disturb experienced by the group ofmemory cells responsive to the programming pulse; and wherein thecontroller is configured to determine a program window responsive to theamount of disturb.
 2. The memory device of claim 1, wherein thecontroller is configured to use the program window during a readoperation to determine voltage ranges in which programmed states arelocated.
 3. The memory device of claim 1, wherein the controller isconfigured to determine the program window prior to each programmingoperation of the group of memory cells.
 4. The memory device of claim 1,wherein the controller is configured to determine the program windowafter a particular number of program operations.
 5. The memory device ofclaim 1, wherein the controller is configured to determine the programwindow aperiodically such that the controller is configured to determinethe program window more frequently as the group of memory cellsexperiences a greater number of program/erase cycles.
 6. The memorydevice of claim 1, wherein the controller is configured to determine theprogram window aperiodically such that the controller is configured todetermine the program window less frequently as the group of memorycells experiences a greater number of program/erase cycles.
 7. Thememory device of claim 1, wherein the controller is configured todetermine the program window during a wear leveling routine.
 8. Thememory device of claim 1, wherein the controller being configured todetermine the amount of disturb experienced by the group of memory cellsresponsive to the programming pulse comprises the controller beingconfigured to determine the amount of disturb experienced by the groupof memory cells responsive to the programming pulse while the group ofmemory cells is at a lowest state.
 9. The memory device of claim 1,wherein the controller being configured to determine the amount ofdisturb experienced by the group of memory cells responsive to theprogramming pulse comprises the controller being configured to determinethe amount of disturb experienced by the group of memory cellsresponsive to the programming pulse while the group of memory cells isat an erased state.
 10. The memory device of claim 1, wherein thecontroller being configured to determine the amount of disturbexperienced by the group of memory cells responsive to the programmingpulse comprises the controller being configured to determine the amountof disturb experienced by the group of memory cells responsive to theprogramming pulse before the group of memory cells is coarse programmed.11. The memory device of claim 1, wherein the controller is configuredto cause the memory device to store the program window in the group ofmemory cells.
 12. The memory device of claim 1, wherein the controllerbeing configured to determine the amount of disturb experienced by thegroup of memory cells responsive to the programming pulse comprises thecontroller being configured to determine a difference between an initialdistribution of a particular state of the group of memory cells prior toapplication of the programming pulse and a final distribution of theparticular state of the group of memory cells after application of theprogramming pulse.
 13. A memory device, comprising: a controller;wherein the controller is configured to cause the memory device to biasall data lines that are coupled to a group of memory cells with aninhibit voltage to inhibit programming of the group of memory cells;wherein the controller is configured to cause the memory device to applya programming pulse to control gates of the group of memory cells;wherein the controller is configured to determine an amount of disturbexperienced by the group of memory cells responsive to the programmingpulse; and wherein the controller is configured to determine a programwindow responsive to the amount of disturb.
 14. The memory device ofclaim 13, wherein the controller being configured to determine theprogram window responsive to the amount of disturb comprises thecontroller being configured to access a table with the amount of programdisturb.
 15. The memory device of claim 13, wherein the controller beingconfigured to cause the memory device to bias all the data lines thatare coupled to the group of memory cells with the inhibit voltagecomprises the controller being configured to cause the memory device tobias all the data lines that are coupled to the group of memory cellswith an inhibit voltage when the group of memory cells is at a loweststate.
 16. The memory device of claim 13, wherein the controller isconfigured to determine that the group of memory cells is unusable inresponse to the program window.
 17. A memory device, comprising: acontroller; wherein the controller is configured to cause the memorydevice to inhibit programming of a group of memory cells while the groupof memory cells is at a lowest state; wherein the controller isconfigured to cause the memory device to apply a programming pulse tocontrol gates of the group of memory cells; wherein the controller isconfigured to determine an increase in threshold voltage experienced bythe group of memory cells responsive to the programming pulse todetermine an amount of disturb experienced by the group of memory cellsresponsive to the programming pulse; and wherein the controller isconfigured to determine a program window responsive to the amount ofdisturb.
 18. The memory device of claim 17, wherein the controller beingconfigured to determine the program window responsive to the amount ofdisturb comprises the controller being configured to access a table withthe increase in threshold voltage experienced by the group of memorycells responsive to the programming pulse.
 19. The memory device ofclaim 17, wherein the controller being configured to determine theprogram window responsive to the amount of disturb comprises thecontroller being configured to determine a voltage.
 20. The memorydevice of claim 17, wherein the controller being configured to determinethe program window responsive to the amount of disturb comprises thecontroller being configured to determine a digital indication of avoltage.